1. Field of the Invention
The present invention relates to a stereo demodulator and a demodulating method thereof and particularly to a stereo demodulator and a demodulating method thereof for demodulating right and left stereophonic signals from a stereophonic composite signal of a pilot tone system transmitted by FM (frequency modulation) radio broadcasting.
2. Description of the Prior Art
An FM stereophonic broadcasting system is known as a broadcasting system for reproducing an audio signal having three-dimensional ranges.
One of the FM stereophonic broadcasting systems is a pilot tone system (a suppressed-carrier AM-FM system) for transmitting a signal having a frequency spectrum as shown in FIG. 1.
Referring to FIG. 1, a stereophonic signal of a pilot tone system includes a main channel of a frequency band of 15 kHz or less and a subchannel of a frequency band of 23 kHz to 53 kHz. A sum signal (L+R) is allotted to the main channel. In the sum signal, the L signal represents a left stereophonic signal and the R signal represents a right stereophonic signal. The subchannel transmits a suppressed-carrier modulated wave (a double side band wave of 38 kHz as a carrier) based on a difference signal (L-R). A pilot signal of a frequency of 19 kHz, i.e., 1/2 of 38 kHz is added for the purposes of identification of a monophonic or stereophonic broadcasting signal and compatible demodulation of the monophonic/stereophonic broadcasting signal. The main channel, the subchannel and the pilot signal are transmitted in a form in which those signals are frequency divided and multiplexed as one radio wave (a main carrier). This multiplexed signal is called a stereophonic composite signal, which is represented by the following equation. EQU A(t)=(L+R)+(L-R) cos .omega.t+P cos (.omega.t/2)
where L and R represent respective amplitudes of the L signal and the R signal, .omega. represents an angular frequency of the subcarrier and P represents an amplitude of the pilot signal.
This stereophonic composite signal is received by an FM receiver. The stereophonic composite signal obtained at an output of an FM detecting circuit included in the FM receiver is demodulated by a stereo demodulator as shown in FIG. 2.
Referring to FIG. 2, a signal input stage of the FM receiver includes a radio-frequency amplifier 101, a frequency converting/intermediate frequency amplifier 102 and an FM detector 103. The FM detector 103 outputs a desired stereophonic composite signal from an amplified intermediate frequency signal.
The stereo demodulator comprises a composite signal amplifier 401 for amplifying a composite signal from the FM detector, a subchannel demodulator 405 and a PLL (phase-locked loop) 407 for providing two kinds of difference signals, and matrix circuits 408 and 409 for providing an L signal and an R signal.
The output composite signal of the composite signal amplifier 401 is supplied to a separation adjuster 403. The separation adjuster 403 adjusts a magnitude of the sum signal (L+R) contained in the composite signal supplied thereto, thereby to adjust separation between the sum signal and the difference signals, that is, separation between the right and left stereophonic signals.
The PLL 407 provides a reproduced subcarrier of 38 kHz in phase locked with that of the pilot signal in the composite signal.
The subchannel demodulator 405 demodulates a difference signal of a positive polarity (L-R) and a difference signal of a negative polarity -(L-R) by using a carrier-suppressed double side band (DSB) signal from the composite signal amplifier 401 and the reproduced subcarrier from the PLL 407.
The matrix circuit 408 receives the sum signal (L+R) from the separation adjuster 403 and the difference signal (L-R) from the subchannel demodulator 405 and performs matrix processing, that is, addition, so as to provide the left stereophonic signal L. The matrix circuit 409 performs matrix processing of the sum signal (L+R) and the negative difference signal -(L-R) and provides the right stereophonic signal R.
The left and right stereophonic signals L and R from the matrix circuits 408 and 409 are supplied to de-emphasis circuits 410 and 411, respectively, where those signals are de-emphasized and unnecessary high-frequency components are removed therefrom.
In the above described construction, at the time of receiving a monophonic broadcast, a monophonic signal is transmitted by the main channel but a stereophonic subchannel signal and a pilot signal are not transmitted. Accordingly, the same monophonic signal (L+R) is obtained from the outputs of the de-emphasis circuits 410 and 411.
FIG. 3 is a circuit diagram showing an example of a concrete construction of the above described stereo demodulator, which is indicated for example in "'85 Sanyo Semiconductor Handbook, Monolithic Bipolar Integrated Circuits", page 360, issued Mar. 20, 1985.
Referring to FIG. 3, the stereo demodulator comprises an amplifier 2 for amplifying a stereophonic composite signal supplied through an input terminal 1, a block 50 for providing a sum signal (L+R), a block 60 for providing two kinds of difference signals (L-R) and -(L-R), a matrix circuit 90 for performing matrix processing of the sum signal and the difference signals from the blocks 50 and 60 to provide right and left stereophonic signals R and L, and an output circuit 80 for receiving the output of the matrix circuit 90 and providing the same to a succeeding stage, for example, a low-frequency amplifier (not shown).
The sum signal circuit block 50 comprises npn bipolar transistors 7 and 8 receiving the stereophonic composite signal from the amplifier 2 at their bases and generating the sum signal (L+R) at their collectors. The transistor 7 has its collector connected to a node N1 and its emitter connected to a ground potential through a resistor R1 and a variable resistor R3. The transistor 8 has its collector connected to a node N2 and its emitter connected to the ground potential through resistors R2 and R3. The variable resistor R3 together with the resistors R1 and R2 adjust the gains of the transistors 7 and 8.
The difference signal demodulating circuit block 60 comprises a first differential circuit 3 for receiving the stereophonic composite signal from the amplifier 2 as an input signal, a PLL circuit 14 for providing a switching signal of 38 kHz in phase locked with that of the pilot signal of 19 kHz and second and third differential circuits 4 and 5 for demodulating the difference signals according to the output of the first differential circuit 3 in response to the switching signal from the PLL circuit 14.
The first differential circuit 3 comprises npn bipolar transistors 12 and 13. The transistor 12 has its base connected to an output of the amplifier 2, its emitter connected to a constant current source 21 through a resistor 10 and its collector outputting an inverted signal of the output of the amplifier 2. The transistor 13 has its base connected to a reference bias power supply +B, its emitter connected to the constant current source 21 through a resistor 11 and its collector for generating a non-inverted signal of the output from the amplifier 2.
The second differential circuit 4 comprises npn bipolar transistors 15 and 16. The transistor 15 has its base receiving a signal of 38 kHz of a first polarity from the PLL circuit 14, its emitter connected to the transistor 12 and its collector connected to the node N1. The transistor 16 has its base receiving a switching signal of 38 kHz of a second polarity from the PLL circuit 14, its emitter connected to the collector of the transistor 12 and its collector connected to the node N2. The switching signals of the first and second polarities from the PLL circuit 14 have opposite phases, namely, the phases different with each other by 180.degree.. The second differential circuit 4 multiplies the switching signal from the PLL circuit 4 by the collector output of the transistor 12 of the first differential circuit 3 and outputs the result of the multiplication. Accordingly, if the difference signal -(L-R) is generated at the collector output of the transistor 15, the difference signal (L-R) of the opposite phase is provided at the collector output of the transistor 16.
The third differential circuit 5 comprises npn bipolar transistors 17 and 18. The transistor 17 has its base receiving the switching signal of the second polarity from the PLL circuit 14, its emitter connected to the collector of the transistor 13 and its collector connected to the node N1. The transistor 18 has its base receiving the switching signal of the first polarity from the PLL circuit 14, its emitter connected to the collector of the transistor 13 and its collector connected to the node N2. Accordingly, in the same manner as in the second differential circuit 4, the collectors of the transistors 17 and 18 provide the difference signals of the opposite phases. According to the above described example, the difference signal -(L-R) is provided at the collector output of the transistor 17 and the difference signal (L-R) is provided at the collector output of the transistor 18.
The matrix circuit 90 performs matrix processing, namely, addition of the sum signal (L+R) from the sum signal circuit block 50 and the two difference signals (L-R) and -(L-R) from the difference signal demodulating circuit block 60, thereby to provide right and left stereophonic signals R and L.
The output circuit block 80 comprises two current mirror circuits. The first current mirror circuit comprises pnp bipolar transistors Tr1 and Tr2. The transistor Tr2 has its base and collector connected to the node N1 and its emitter connected to a power supply potential +Vcc. The transistor Tr1 has its emitter connected to the power supply potential +Vcc, its base connected to the node N1 and its collector connected to an output terminal 19. The output terminal 19 is provided with a resistor R4 for converting collector current of the transistor Tr1 to a voltage signal. In the first current mirror circuit, collector current equal to the collector current of the transistor Tr2 flows through the transistor Tr1.
The second current mirror circuit comprises a diode-connected pnp bipolar transistor Tr3 and a pnp bipolar transistor Tr4 for output. The transistor Tr3 has its base and collector connected to the node N2 and its emitter connected to the power supply potential +Vcc. The transistor Tr4 has its emitter connected to the power supply potential +Vcc, its base connected to the node N2 and its collector connected to an output terminal 20. The output terminal 20 is connected with a resistor R5 for current-voltage conversion. The resistor R5 is connected between the output terminal 20 and the ground potential. Also in the second current mirror circuit, equal collector current flows in the transistors Tr3 and Tr4.
Now, operation will be briefly described.
The transistors 7 and 8 receive the stereophonic composite signal from the amplifier 2 at their respective bases and generate the sum signal (L+R) of the main channel at their respective collectors. The first differential circuit 3 receives the output from the amplifier 2 at the base of the transistor 12. The emitters of the transistors 12 and 13 are connected to the constant current source 21 through the resistors 10 and 11, respectively and the base of the transistor 13 is connected to the reference bias power supply +B. When no signal is applied, the base voltages of the transistors 12 and 13 of the first differential circuit 3 are equal to each other and the respective emitter currents thereof are also equal to each other. When the stereophonic composite signal from the amplifier 2 becomes larger than the reference voltage +B, the emitter current i1, namely, the collector current of the transistor 12 increases. In the opposite case, the emitter current i1 of the transistor 12 (the collector current) decreases. The sum of the emitter currents of the transistors 12 and 13 is equal to a constant current I flowing in the constant current source 21. Consequently, the collectors of the transistors 12 and 13 provide, as the collector currents, subchannel subcarrier-suppressed difference signal components of opposite phases.
In the second and third differential circuits 4 and 5, the signals of 38 kHz of the opposite phases are supplied from the PLL circuit 14 to the respective bases of the transistors 15 and 18, and 16 and 17. Accordingly, the transistors 15 and 18 are simultaneously turned on and, on the other hand, the transistors 16 and 17 are simultaneously turned on. The conduction of the transistors 15 and 18 and the conduction of the transistors 16 and 17 occur alternately. The emitters of the transistors 15 and 16 are connected to the collector of the transistor 12, while the emitters of the transistors 17 and 18 are connected to the collector of the transistor 13. Accordingly, in the second and third differential circuits, the opposite difference signals (L-R) and -(L-R) are generated at the collectors of the transistors simultaneously turned on. The second and third differential circuits demodulate the two difference signals by multiplying the switching signal from the PLL circuit 14 by the output of the first differential circuit 3.
The matrix circuit 90 performs addition of the sum signal and the difference signals supplied to the nodes N1 and N2. As a result, the left and right stereophonic signals L and R are generated at the nodes N1 and N2 in the form of current signals.
In the output circuit 80, collector currents equal to those of the transistors Tr2 and Tr3 are generated at the collectors of the transistors Tr1 and Tr4, respectively. The collector currents of the transistors Tr1 and Tr4 are converted to voltage signals by the resistors R4 and R5, respectively, and the converted signals are outputted as the left stereophonic signal L and the right stereophonic signal R from the output terminals 19 and 20, respectively.
In the above described conventional stereo demodulator, the transistors 7, 8, 12 and 13 in the input stage are adapted to operate in a linear region by application of voltage. However, the V.sub.BE -I.sub.C characteristic of the transistors exhibit non-linear rising characteristics. More specifically, a region near the cut-off region of the transistors exhibit characteristic curves greatly deviated from a straight line. In consequence, a non-linear distortion occurs in the base-emitter voltage of each of the transistors 7, 8, 12 and 13, which causes deterioration of linearity of the stereo demodulator, that is, deterioration of a distortion factor, making it difficult to reproduce the right and left stereophonic signals correctly.
In order to operate the first differential circuit 3 in the linear region, the maximum level of the input signal applied to the base of the transistor 12 should be limited. Accordingly, the dynamic range is limited, and the input signal level range providing a good S/N (signal-to-noise) ratio is also restricted. For example, assuming that the reference DC voltage +B applied to the base of the transistor 13 is +3V, that the values of the emitter resistors 10 and 11 are both 1 k.OMEGA., and that the constant current I flowing in the constant current source 21 is 1 mA, the maximum level of the input signal is 1V.sub.p (700Vrms) with respect to the DC voltage +B as a reference voltage and if a larger signal is applied, deterioration of the S/N ratio can not be avoided.